The present disclosure relates to a semiconductor device and a method for making the device.
Recently, as the performances and functionalities of semiconductor devices have been further enhanced, there have been growing demands for 3D die stacking technologies for stacking a plurality of chips (dies) vertically one upon the other as a possible replacement for conventional 2D implementation technologies, which are typically implemented as a system on chip (SoC), for example. Among other things, 3D die stacking technologies for semiconductor chips with through electrodes (which are typically configured as “through silicon vias (TSVs)”) have been developed particularly extensively. However, those 3D die stacking technologies for semiconductor chips with through electrodes are not without serious problems. One of those serious problems is an increase in manufacturing cost. Thus, to cut down the manufacturing cost, wafer-on-wafer stacking has attracted a lot of attention these days as an alternative to the conventional chip-on-chip stacking technique.
To make wafer-on-wafer stacking, however, each pair of chips provided on two wafers to be stacked one upon the other need to have exactly the same size and pitch. For that reason, when two chips of the same kind with exactly the same chip size, such as two memory chips, are going to be stacked one upon the other, wafer-on-wafer stacking is not so difficult a hurdle to overcome. However, if two chips of mutually different kinds, such as a memory chip and a logic chip or a digital chip and an analog chip, are going to be stacked one upon the other, at least one of the two wafers should have a dead zone. The reason is that the size and pitch of each chip on one wafer need to be the same as those of its associated chip on the other wafer. This increases the cost inevitably. On top of that, unless the wafer-on-wafer stacking process is designed cooperatively with not only the chip sizes and pitches but also electrode layouts and all the other parameters coordinated with each other, it is difficult to carry out the wafer-on-wafer stacking process.
Thus, in order to carry out a wafer-on-wafer stacking process even when the chips are not designed cooperatively, somebody proposed a stacking method using a wafer expanded with a resin (see, for example, N. Maeda et al., Development of Ultra-Thin Chip-on-Wafer Process Using Bumpless Interconnects for Three-Dimensional Memory/Logic Applications, Symposium on VLSI Technology, Digest of Technical Papers, pp. 171-172, 2012). Such a wafer expanded with a resin (which will be hereinafter referred to as a “resin-expanded wafer”) is obtained by rearranging a number of chips, which have been cut out of one of the two wafers, on a supporting wafer so that those chips have the same pitch as chips on the other wafer, filling the gap between the chips with a resin, and then planarizing the upper surface. People hope that the wafer-on-wafer stacking process could be carried out by using such a resin-expanded wafer, even if the chips are not designed cooperatively.